1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an erasable programmable read only memory.
2. Description of Related Art
EPROM, an acronym for Erasable Programmable Read Only Memory, is the memory circuit that is most often used in computer and electronic products. One of its advantages is that neither the program, nor the data stored in the EPROM, will not be lost under normal conditions. If there is a need to erase the stored program and data, it is simply exposed to an ultraviolet light source for a specified period of time. In this way, the EPROM can be reprogrammed again. However, the EPROM erase operation will wipe out all the stored data residing within. Therefore, whenever data update is required, every bit of data must be rewritten back to the EPROM, which is rather time consuming. Intel Corporation developed flash EPROM technology. In flash EPROM, the data does not need to be completely erased. Instead, the characteristic of the flash EPROM is to erase data block by block. Hence, the time for reprogramming a flash EPROM is reduced.
An Intel type flash EPROM cell is incorporated within the EPROM. The erasing step is performed in the source regions of the flash memory cell. In the conventional method of fabricating a flash memory cell, it is easy to form silicide layers on the source regions. The silicide formations on source regions will cause current leakage and reduce the endurance of components.
FIG. 1 is a top-view of a layout showing a conventional flash memory cell. In FIG. 1, the conventional flash memory cell includes a field oxidation 101, a floating gate layer 103, a control gate 105, a mask layer 106, a drain region 109, and a common source region 108. The mask layer 106 is used for a self-align source (SAS) etching step.
FIGS. 2A through 2E are cross-sectional views of a portion of a semiconductor device showing the conventional steps of fabricating a flash memory cell. The (I) of each figure is a cross-sectional view of FIG. 1 taken along line I--I. The (II) of each figure is a cross-sectional view of FIG. 1 taken along line II--II. The (III) of each figure is a cross-sectional view of FIG. 1 taken along line III--III.
In FIG. 2A, a P-type substrate 100 having a field oxidation 101 thereon is provided. A tunnel oxide layer 102 and a floating gate layer 103 are formed sequentially over the substrate 100, in which tunnel oxide layer 102 and the floating gate layer 103 are patterned.
In FIG. 2B, an isolation layer 104 and a control gate layer 105 are formed sequentially over the substrate 100. The control gate layer 105, the isolation layer 104, the floating gate layer 103, and the tunnel oxide layer 102 are patterned.
In FIG. 2C, a mask layer 106 is formed over the substrate 100. The mask layer 106 is used for defining a common source region (See FIG. 2D). The mask layer 106 is used as an etching mask in order to etch a portion of the field oxidation 101, which is exposed by the mask layer 106 thereon. Once the etching step is completed, the field oxidation 101, which is exposed by the mask layer 106 thereon, is removed to expose a portion of the substrate 100. The etching step described above is called a self-align source (SAS) etching step. A source-lightly-doped ion implantation is performed to form an n-doped layer 103 in the substrate 100.
In FIG. 2D, the mask layer 106 is removed. A source-drain ion implantation is performed to form a common source region 108 and a drain region 109 in the substrate 100.
In FIG. 2E, spacers 110 are formed on sidewalls of the control gate layer 105, the isolation layer 104, the floating gate layer 103, and the tunnel oxide layer 102. A salicide step is performed to form silicide layers 111 on the control gate layer 105, the common source region 108, and the drain region 107.
In the conventional method of fabricating a flash memory cell, the silicide layers 111 are formed on a source region, such as the common source regions 108 (shown in FIG. 2E). As is known, the erasing step is performed on the source region. Once the erasing step is performed, the silicide formation on source region causes leakage current. Thus, it reduces the endurance of components.